The present invention relates in general to the field of semiconductor fabrication methodologies and resulting device structures. More specifically, the present invention relates to fabrication methodologies and resulting structures for a semiconductor device having a heterogeneous metal interconnect structure containing both narrow and wide trenches or lines that can be formed simultaneously.
Semiconductor devices and components, which are referred to collectively herein as integrated circuit (IC) components, include a plurality of circuit elements (e.g., transistors, resistors, diodes, capacitors, etc.) communicatively connected together on a semiconductor substrate (i.e., a wafer or a chip). IC components are coupled to one another by providing a network of interconnected metallization layers and conductive trenches formed in the wafer/chip. Metallization layers and trenches are often formed using copper (Cu), which facilitates the development of smaller metal components, reduced energy usage, and higher-performance processors. Efficient routing of these metallization layers and trenches through multi-layered chip designs requires the formation of multi-level or multi-layered metallization layer and trench patterning schemes.